The invention relates to a clock generation circuit.
The invention further relates to an integrated circuit for reproducing an audio signal comprising such a clock generation circuit.
In many electronic circuits, particularly those utilizing digital electronics and computers, it is necessary to produce clock signals having a number of different frequencies. In particular this issue arises in optical recording systems, where different steps in the process of converting an input signal into a write signal have to be synchronized to each other. Said process generally comprises the steps of encoding the input signal with an error correcting code, such as a cross interleaved Reed-Solomon code. Channel encoding the signal so obtained with a channel code, e.g. EFM-modulation. Generating a write signal which achieves that said channel encoded signal is written as accurately as possible at the record carrier. For this purpose a write strategy generator is used which generally requires a clock signal which has a frequency which is significantly higher than the frequency which is used for clocking the channel encoder. Such a write strategy generator is described for example in the non-prepublished patent Application PHN 17747. Often an external phase locked loop is used to generate the clock frequency for the write strategy generator. It has been found necessary to generate a clock signal for said PLL having the same frequency and phase as a reference clock, but has a duty cycle of 50%, independent of the duty cycle of the reference clock.
It is a purpose of the invention to provide a clock generation circuit which generates an output clock having the same frequency and phase as a reference clock, but has a duty cycle of 50%, independent of the duty cycle of the reference clock. In accordance therewith, the clock generation circuit of the invention comprises
an input for receiving an input clock signal
a frequency divider for generating a first intermediate clock signal
a first logical unit for combining the input clock signal and the intermediate clock signal
a clocked bistable unit having a clock input coupled to an output of the first logical unit, and a data input and a data output,
a second logical unit having a selection input for receiving a synchronization signal that controls selection between a feedback mode and a reset mode, in which feedback mode the second logical unit logically inverse couples the data input to the data output, and in which reset mode the second logical unit couples the data input to a synchronization module having an input for receiving a reference clock signal,
an output coupled to the data output for providing the output clock signal.
In the feedback mode the input of the clocked bistable unit is coupled to its data output in a logically inverse sense. Hence, the clocked bistable unit, such as a flip-flop then generates an output signal having half the frequency of the intermediate clock signal, but having a duty cycle of 50%. In the reset mode however, the clocked bistable unit receives a reset value via the second logical unit, which allows the clock generation circuit to synchronize the output clock signal with a reference clock signal.
EP 551 969 A2 describes a clock generation circuit in which a master clock is divided by an odd integral value by a synchronous state machine. Subsequently an output clock having a 50% duty-cycle is generated by combining an output signal of the synchronous state machine with the master clock signal. No means are disclosed for synchronizing the rising edge of the output clock with the rising edge of an input clock having the same frequency as the output clock.
EP 440 357 A2 describes a clock generation circuit which generates a plurality of clock signals from an input clock signal having different phase relationships to the input clock signal. One of the plurality of clock signals which closest matches the phase of the input clock signal is selected. Although the output clock signal has substantially the same frequency and phase as the input clock signal it is not realized therein that the output clock has a 50% duty-cycle independent of the duty-cycle of the input clock.
U.S. Pat. No. 5,999,026 describes a resynchronization device which resynchronizes a binary signal with a clock having a relatively high frequency. The device comprises a resynchronization module, in which the output is coupled to the input which receives the binary signal by a first and a second flip flop of which the first is clocked at the falling edge and the other at the rising edge of the clock. The first flip-flop may be bypassed via a multiplexer. This device does not make it possible to produce an output clock signal having the same frequency and phase as a reference clock signal, but having a duty-cycle of 50% independent of the duty-cycle of said reference clock signal.
In an embodiment the clock generation circuit is characterized in that the synchronization module comprises a third logical unit, a first further clocked bistable unit having a data-input coupled to an output of the third logical unit, a second further clocked bistable unit having a data input coupled to a data output of the first further clocked bistable unit and a third further clocked bistable unit having a data input coupled to a data output of the second further clocked bistable unit, the third logical unit having a first input for receiving a signal which represents the start of a sync procedure, a second input coupled to the data output of the first further clocked bistable unit and a third input coupled to the second further clocked bistable unit for stopping the sync procedure, the input for receiving the reference clock signal being coupled to a clock input of the second further clocked bistable unit.
An embodiment of the clock generation circuit of the invention is characterized in that the first logical unit comprises a further negatively triggered bistable unit and a logical gate, wherein the input clock signal serves as a clock signal for the further negatively triggered bistable unit and wherein the logical gate receives the intermediate clock signal via the further negatively triggered bistable unit as a first input signal and the input clock signal as a second input signal. The combination of the negatively triggered bistable unit and the logical gate ensures that an output signal is generated which is independent of small delays in the intermediate clock signal. The intermediate clock signal therefore need not be balanced.